(a) Field of the Invention
The present invention relates to a method for fabricating a semiconductor device.
(b) Description of the Related Art
Typically, in a metal wiring process for electrically connecting upper and lower metal layers and horizontal wirings, inter metal dielectric layer is formed to isolate the neighbor wirings.
Recently, the inter metal dielectric is formed by depositing dielectric material such as oxide on the semiconductor substrate having a plurality of wirings through a high density plasma process.
However, since the width and pitch of the metal wirings become narrower and lower as the device is highly integrated, the inter metal dielectric formation using the conventional HDP process causes to decrease the area for forming the inter metal dielectric and increase the height, i.e. high aspect ration, thereby voids occurs inside the inter metal dielectric. In this case the voids are filled by conductive material so as to shorten the adjacent devices, resulting in malfunction of the devices.
In order to prevent the voids from occurring inside the inter metal dielectric, a bias power is applied onto the semiconductor substrate in vertical direction while depositing the inter metal dielectric. However, the increase of the bias power applied onto the semiconductor substrate causes an antenna effect due to the plasma such that the metal wirings are partially etched out to cause a corner clipping effect of the metal wirings. This decreases the conductivity of the wirings.
Methods of forming the inter metal dielectrics have been disclosed in the U.S. Pat. Nos. 6,495,478, 6,495,208, and 6,174,800, in which a spin on polymer (SOP), an organic polymer layer, an oxide dielectric and an organic polymer are simultaneously deposited, and other inter metal dielectric is formed through a chemical vapor deposition technique.